High density MOS devices have been increasing use in recent years in both consumer and military applications as a result of the demand for low cost information processing devices. In particular, MOS Random Access Memories (RAM's) constitute some of the densest components of conventional processing systems. As the density of these devices increases, various circuit and system techniques have been developed to maintain or increase performance with respect to that of less dense circuits without decreasing component yields. Yield, in particular, becomes the dominating factor when increasing the number of circuit elements per chip while maintaining or improving circuit operating parameters.
Response time in devices such as MOS RAMs is a function of the memory cell size, the number of cells per bit line and the type of sensing circuit utilized to access data stored in the cells. One example of this is illustrated in U.S. Pat. No. 4,081,701, issued to White et al. on Mar. 28, 1978 and assigned to Texas Instruments Incorporated. The sensing circuit or sense amp of U.S. Pat. No. 4,081,701 accesses data by increasing the sensitivity in discrete steps. In this manner, low signal levels stored in a memory cell can be sensed. All of the sense amps that access data in a selected row of memory elements are controlled by a centralized control circuit which controls current flow through each of the sense amps in discrete steps. Each of these discrete steps has a predetermined duration provided by timing signals from an internal clock circuit, each of the timing signals separated by delays generated internal to the clock circuit. Therefore, the sensitivity of the sense amps and the time required to access data therewith is controlled by this centralized control circuit. The operation of the sense amps is more fully disclosed in U.S. Pat. No. 4,050,061, issued to Kitagawa on Sept. 20, 1977. By varying the sensitivity of the sense amp for each discrete step and the time delay between the steps, access times can be increased or decreased, but not without some trade-offs such as signal margin, pattern sensitivity, etc.
Although the relationship between the various operating parameters of a given MOS circuit is defined in the design stage, variations may result due to processing variations. Attempts are made during the design phase of a circuit to accommodate for these process variations, but in some cases circuit operating parameters must be pushed to their limits, the result being a potentially decreased yield. This decreased yield can be improved with innovative fabrication techniques, but a large number of marginal devices will still be classified as defective. The marginal operating parameters can be the result of very small defects in such circuits as the control circuitry for the MOS RAM. Without some form of adjustment, the marginal device will be discarded.
Heretofore, a number of techniques have been developed in order to provide a more "defect tolerant" device. One such technique utilizes redundant circuits on the chip to replace defective circuits. These redundant circuits can be placed in operation to permanently override the defective circuit portion. Redundant circuits are utilized, for example, to replace defective memory cells. However, the degree of defect tolerance provided by redundant circuitry is a function of the percentage of circuitry on a particular chip that is made redundant which, as a practical consideration, must be minimized. The redundant circuits essentially replace sections of the circuitry rather than modify the actual operating parameters of the circuitry itself. In marginal devices, the defect is usually the result of operating parameters that deviate too far from a predetermined value. Such parameters as access time, signal sensitivity and power dissapation may be the result of a weak device or a timing delay that is too short, consequently causing the device to operate marginally for a particular operation. The use of redundant circuitry to correct marginal operating parameters may not be cost effective in that the defect of the operating device may also be reflected in the redundant device.
In view of the above disadvantages, there exists a need for a method to adjust the operating parameters on a chip to compensate for fabrication variations to both increase yield and to provide increased versatility at the manufacturing level.